1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device including a plurality of memory array blocks.
2. Description of the Background Art
FIG. 13 is a circuit diagram of a portion of a conventional static random access memory (referred to as a SRAM hereinafter). This semiconductor memory device is disclosed in Japanese Patent Laying-Open No. 61-190786.
Referring to FIG. 13, a memory cell array 10 comprises a plurality of word lines WL, a plurality of bit line pairs BL, BL crossing word line WL, and a plurality of memory cells MC provided in the crossings thereof. Memory cell array 10 has a structure of four rows and four columns. Each bit line pair BL, BL is connected to a first voltage supply line V1 via bit line load transistors Q11 and Q12. Each bit line pair BL, BL is connected to input/output line pair I/O, I/O via transfer gate transistors Q13, Q14.
An X decoder 20 is responsive to an X address signal to provide a signal for activating word line selecting circuit 40. Word line selecting circuit 40 comprises a plurality of NOR gates G2 corresponding to the plurality of word lines WL. The output of each NOR gate G2 is provided to the corresponding word line WL. A Y decoder 30 is responsive to a Y address signal to provide a signal to activate a bit line selecting circuit 60. Bit line selecting circuit 60 comprises a plurality of NOR gates G3 corresponding to the plurality of bit line pairs BL, BL. The output of each NOR gate G3 is provided to the gates of the corresponding transfer gate transistors Q13, Q14.
Input/output line pair I/O, I/O is connected to local sense amplifier LSA of the differential amplification type and a write driver WD. Local sense amplifier LSA and write driver WD form a read/write amplifying circuit 50.
Local sense amplifier LSA comprises bipolar transistors Q21, Q22 and an N channel MOS transistor Q23. Local sense amplifier LSA is responsive to the output of sense amplifier selecting circuit 70 to be activated for detecting and amplifying the potential difference between input/output line pair I/O and I/O. The amplified potential difference is provided to read data buses Ra, Rb.
Write driver WD comprises N channel MOS transistors Q31-Q34. Transistor Q31 is connected between the first voltage supply line V1 and input/output line I/O. Transistor Q33 is connected between the first voltage supply line V1 and input/output line I/O. Transistor Q32 is connected between a second voltage supply line V2 and input/output line I/O. Transistor Q34 is connected between the second voltage supply line V2 and input/output line I/O. Transistors Q31 and Q34 have their gates connected to write data bus Wa. Transistors Q32 and Q33 have their gates connected to write data bus Wb. Write data buses Wa and Wb are supplied with the output of write amplifier 80.
An output circuit 90 is connected to read data buses Ra, Rb. Output circuit 90 comprises a clamp potential generating circuit CL, a main sense amplifier MSA of the current detection type, and an ECL level output circuit OC.
Clamp potential generating circuit CL comprises a diode D1, a bipolar transistor Q41, and a resistor R1. Diode D1 is connected between first voltage supply line V1 and the collector of transistor Q41. The base of transistor Q41 is supplied with reference potential VR for constant current generation. The emitter of transistor Q41 is connected to second voltage supply line V2 via resistor R1. Transistor Q41 and resistor R1 form a constant current source.
Main sense amplifier MSA comprises transistors Q42 and Q43 for read data bus clamping, emitter follower transistors Q44 and Q45, diodes D2 and D3 for level shifting, resistors R2 and R3, and constant current sources CS1-CS4. Transistors Q42, Q43 have their collectors connected to first voltage supply line V1 via resistors R2 and R3, respectively. The output of clamp potential generating circuit CL is provided to the bases of transistors Q42 and Q43. The emitter of transistor Q42 is connected to read data bus Rb and constant current source CS1. The emitter of transistor Q43 is connected to read data bus Ra and constant current source CS2. Transistors Q44 and Q45 have their bases supplied with the outputs of resistors R2 and R3, respectively. The emitter of transistor Q44 is connected to constant current source CS3 via diode D2. The emitter of transistor Q45 is connected to constant current source CS4 via diode D3.
ECL level output circuit OC comprises bipolar transistors Q51-Q54 and resistors R4, R5. The base of transistor Q51 is supplied with the output of diode D3. The base of transistor Q52 is supplied with the output of diode D2. The base of transistor Q53 is supplied with reference potential VR. Data output is obtained from the emitter of transistor Q54.
FIGS. 14 and 15 are circuit diagrams showing examples of the structures of a memory cell MC. FIG. 14 shows a high resistance load type NMOS memory cell. FIG. 15 shows a CMOS type memory cell.
The memory cell of FIG. 14 comprises N channel MOS transistors Q1-Q4 and load resistors R6 and R7. Complementary data are held in nodes N1 and N2.
The memory cell of FIG. 15 comprises N channel MOS transistors Q1-Q4 and P channel MOS transistors Q5 and Q6. Similarly, complementary data are held in nodes N1 and N2 in this memory cell.
FIG. 16 is a circuit diagram showing the main components of FIG. 13. The operation of the SRAM of FIG. 13 will be explained hereinafter with reference to FIG. 16.
When a signal of low level is applied to the two input terminals of one of NOR gates G2 in word line selecting circuit 40 from X decoder 20, the potential of word line WL attains a high level. At this time, a signal of high level is applied to at least one of the two input terminals of the other NOR gates G2 in word line selecting circuit 40. Accordingly, the potentials of the other word lines WL are at a low level. A signal of low level is applied to the two input terminals of one of NOR gates G3 in bit line selecting circuit 60 from Y decoder 30. The output of that NOR gate G3 attains a high level, whereby the corresponding transfer gate transistors Q13 and Q14 are turned on. As a result, one of the memory cells MC is selected.
It is assumed that the potential of node N1 in memory cell MC is held at a high level, and the potential of node N2 is held at a low level. Transistor Q1 is non conductive, and transistor Q2 is conductive at this time.
At the time of data reading, the outputs of write amplifier 80 are both fixed at the low level. When the potential of word line WL is at a high level, transfer gate transistors Q3 and Q4 in memory cell MC are both conductive.
Assume that the potential of first voltage supply line V1 is ground potential (=0 V), and the potential of second voltage supply line V2 is V.sub.EE (-5.2 V when ECL 10 K). Because N channel MOS transistor is used as a load, potential V.sub.B1 of bit line BL attains a level lower than ground potential by threshold voltage Vth of N channel MOS transistor. Accordingly, EQU V.sub.B1 =-Vth
Potential V.sub.B2 of bit line BL is reduced by .DELTA.V due to the ON resistance of bit line load transistor Q12. Therefore, EQU V.sub.B2 =-Vth-.DELTA.V
.DELTA.V is called the bit line voltage swing, which is normally 50 mV to 500 mV. This bit line amplitude is adjusted by the size of the bit line load transistor.
The bit line voltage swing appears on input/output line pair I/O, I/O via transfer gate transistors Q13 and Q14. This bit line voltage swing is amplified by local sense amplifier LSA to be provided to read data buses Ra and Rb as current output. Since the potentials of bit lines BL and BL are at a high level V.sub.b1 and a read low level V.sub.B2, respectively, at this time, the potentials of input/output lines I/O and I/O are at a high level and a read low level, respectively. Therefore, only transistor Q21 conducts, whereby sense current flows through read data bus Ra. Current does not flow through read data bus Rb.
The potentials of read data buses Ra and Rb are clamped at a constant clamp potential V.sub.CL by clamp potential generating circuit CL and clamp transistors Q42 and Q43. Clamp potential V.sub.CL is defined by the output potential (-V.sub.D) of clamp potential generating circuit CL and voltage V.sub.BE between the bases and emitters of clamp transistors Q42 and Q43, expressed as follows. EQU V.sub.CL =-V.sub.D -V.sub.BE
In main sense amplifier MSA, sense current flows to resistor R3 through clamp transistors Q43. Therefore, the output of resistor R3 is lower in voltage than the output of resistor R2 by sense current. Accordingly, potential of a low level is provided from resistor R3.
The potential difference between the outputs of resistors R2 and R3 is provided to ECL level output circuit OC via emitter follower transistors Q44, Q45 and level shift diodes D2, D3. Data of ECL level is provided by ECL level output circuit OC. Thus, the read operation is carried out.
At the time of data writing, potential of one bit line is pulled to a write low level (V.sub.EE), and the potential of the other bit line is pulled up to a high level. In the case of writing an inverted data to memory cell MC in FIG. 16, the potential of write data bus Wa is brought to a low level by write amplifier 80, and the potential of write data bus Wb is turned to a high level. This causes transistors Q31 and Q34 in write driver WD to go into non-conduction, and transistors Q32 and Q33 to go into conduction. Accordingly, the potential of input/output line I/O attains a low level, and the potential of input/output line I/O attains a high level. As a result, the potential of bit line BL attains a low level, and the potential of bit line BL attains a high level. Thus, the writing operation is carried out.
In the above described SRAMs, a structure of dividing the memory array into a plurality of blocks is employed using divided word line techniques to comply with increase in integration density. This divided word line technique is disclosed in Japanese Patent Publication No. 62-28516, for example.
For the purpose of reducing the number of bit line pairs connected to the same input/output line pair for preventing the access time from increasing, and for the purpose of simplifying the switching of the data organization on the same chip (for example, 1 bit organization and 4 bit organization), each block is divided into 4-16 sub-blocks, with 4-16 local sense amplifiers disposed corresponding to the 4-16 sub-blocks. By multiplexing the outputs of these local sense amplifiers, data output of 1 bit can be obtained.
FIGS. 17-21 are block diagrams showing an example of a semiconductor memory device having a memory cell array divided into the above-described blocks and sub-blocks. In this embodiment, the memory cell array is divided into 8 blocks, where each block is further divided into 4 sub-blocks.
Referring to the semiconductor memory device of FIG. 17, an X decoder 2 acting as a main word line driving circuit is disposed at the end of a memory cell array 1a.
Memory cell array 1a is divided into 8 blocks BK1-BK8 using the divided word line technique. Each block is divided into four sub-blocks S0-S3. Four read/write amplifying circuits A0-A3 are disposed corresponding to the four sub-blocks S0-S3. The read/write amplifying circuit comprises local sense amplifier LSA and write driver WD shown in FIG. 13.
Eight word line selecting circuits 41-48 are provided corresponding to the eight blocks of BK1-BK8. A block selector 3a is disposed at one side of memory cell array 1a. The output signals of block selector 3a are applied to word line selecting circuits 41-48 via the respective block selecting lines BS1-BS8.
At the other side of memory cell array 1a, four input/output circuits IO0-IO3 corresponding to a 4-bit data are disposed. The four read/write amplifying circuits A0-A3 corresponding to each of blocks BK1-BK8 are connected to four input/output circuits IO0-IO3 via four sets of read/write data buses (referred to as data buses hereinafter) RW0-RW3.
To simplify the drawing, Y decoder 30 and bit line selecting circuit 60 (refer to FIG. 13) are omitted.
The operation of the semiconductor memory device of FIG. 17 will be explained briefly. The operation of the circuit of the Y address system is referred to that regarding FIG. 13, and will be not repeated here.
In a semiconductor memory device using the divided word line technique, only one of the plurality of blocks is activated by the output signal of block selector 3a. Referring to FIG. 17, one of the plurality of output signals of X decoder 2 and one of the plurality of output signals of block selector 3a are selected. The combination of these two output signals select one word line (local word line) in one block.
Consider a case where block BK1, for example, is selected. The signal of block selecting line BS1 is activated by block selector 3a. Also, one of the plurality of output signals of X decoder 2 is activated. As a result, one local word line in block BK1 is driven. This selects a plurality of memory cells connected to that local word line.
At this time, read/write amplifying circuits A0-A3 corresponding to block BK1 are activated. Read/write amplifying circuits A0-A3 corresponding to the other blocks BK2-BK8 are not activated. As a result, read/write operation of data is carried out via data buses RW0-RW3 between read/write amplifying circuits A0-A3 corresponding to block BK1 and input/output circuits IO0-IO3.
Only one block in the memory cell array divided into a plurality of blocks is activated to carry out read/write operation in a semiconductor memory device using the divided word line technique.
Referring to the semiconductor memory device of FIG. 18, an X decoder is disposed in the center of memory cell array 1a. Blocks BK1-BK4 are disposed at one side, and blocks BK5-BK8 are disposed at the other side.
Referring to the semiconductor memory device of FIG. 19, memory cell array la is divided into two by dividing each bit line pair at the center. X decoders 2a and 2b are arranged in the center of memory cell array 1a. Blocks BK1, BK2 are disposed at one side of X decoder 2a, and blocks BK5, BK6 are disposed at the other side. Blocks BK3, BK4 are disposed at one side of X decoder 2b, and blocks BK7, BK8 are disposed at the other side.
Referring to the semiconductor memory device of FIG. 20, X decoder 2 is disposed at one end of memory cell array 1a. A block selector 3a is disposed at the other end.
Referring to the semiconductor memory device of FIG. 21, an X decoder.sup.. block selector 23a including an X decoder and a block selector is disposed in the middle of memory cell array 1a. Blocks BK1-BK4 are arranged at one side of X decoder.sup.. block selector 23a, and blocks BK5-BK8 are disposed at the other side.
The structures of the components in the semiconductor memory devices of FIGS. 18-21 are similar to those in the semiconductor memory device of FIG. 17. Only the arrangement of the components differs. The operation of the semiconductor memory devices of FIGS. 18-21 is similar to that of the semiconductor memory device of FIG. 17.
In the semiconductor memory devices of FIG. 17-21, data buses RW0-RW3 are arranged along the direction of the longer side of chip CH. This is responsible for the lengthy wiring of data buses RW0-RW3. The load capacitance of each data bus is also increased. This leads to a problem that the delay time of the signals in data buses RW0-RW3 is increased.
In order to reduce the wiring length of each read data bus, a method of dividing each read data bus into a plurality of wiring portions is employed, as disclosed in Japanese Patent Laying-Open No. 2-101697, for example.
However, this method will result in increase in the width of the wiring region for the data bus if the data organization (bit width) is increased, such as to a 4-bit organization, an 8-bit organization, a 16-bit organization. Two wirings are respectively necessary for each read data bus and each write data bus. In the case of 16-bit organization, a total of 64 wirings will be arranged along the longer side of the chip. This yields a second problem that a large wiring region is necessary on the chip.
If the block selector is arranged in a direction identical to the X decoder, as in the semiconductor memory devices of FIGS. 20 and 21, the length of block selecting lines BS1-BS8 transmitting the output signal of the block selector depends on the distance to the block to be driven. This results in difference in the wiring length between block selecting lines BS1-BS8. This difference in wiring length causes great difference in the load capacitance of the block selecting line. This will cause skew of the output signals of the block selector in the semiconductor memory device.
Referring to FIG. 22, there is a skew time t1 between the potential of block selecting line BS5 dropping from a high level to a low level and the potential of block selecting line BS1 attaining a high level from a low level. This means that there is a time period where no memory cell is selected in the blocks.
Referring to FIG. 23, there is a time period t2 where the potential of block selecting line BS1 and the potential of block selecting line BS5 both are at a high level. This causes a double or multi-selection state where memory cells in a plurality of blocks are selected at the same time.
This causes erroneous writing at the time of data writing. The access time at data reading will also be increased.